1. Field of the Invention
The present invention relates to a chip package structure, and more particularly, to a chip package structure having a bus bar.
2. Description of Related Art
In the semiconductor manufacturing industry, the production of integrated circuits (IC) is mainly divided into three major stages: the integrated circuit (IC) design stage, the IC fabrication stage and the IC packaging stage.
In the integrated circuit (IC) fabrication stage, a series of processes including wafer manufacturing, integrated circuit forming and wafer sawing is sequentially performed in order to fabricate the chips. The wafer has an active surface, where active devices are formed. After forming all the integrated circuits on the wafer, a number of bonding pads is disposed on the active surface of the wafer so that each chip cut out from the wafer can electrically connect with an external carrier through these bonding pads. The carrier may be a lead frame or a package substrate. The chip can be electrically connected to the carrier by wire bonding or flip-chip bonding method so that the bonding pads on the chip are electrically connected to their corresponding contacts on the carriers to produce a chip package structure.
FIG. 1 is a top view of a conventional chip package. FIG. 2 is a schematic cross-sectional view of the chip package in FIG. 1. To facilitate the following description, the encapsulant 140 of the package is transparent in FIGS. 1 and 2 and the profile of the encapsulant 140 is outlined by dash lines. As shown in FIGS. 1 and 2, the chip package 100 includes a lead frame 110, a chip 120, a plurality of first bonding wires 130, a plurality of second bonding wires 132, a plurality of third bonding wires 134 and an encapsulant 140. The lead frame 110 includes a die pad 112, a plurality of inner leads 114 and a plurality of bus bars 116. The inner leads 114 are disposed around the die pad 112. The bus bars 116 are disposed between the die pad 112 and the inner leads 114. Furthermore, the bus bars 116 and the inner leads 114 are coplanar.
The chip 120 has an active surface 122 and a back surface 124 on the other side. The chip 120 is disposed on the die pad 112 with the back surface 124 facing the die pad 112. The chip 120 has a plurality of ground contacts 126 and a plurality of non-ground contacts 128. The non-ground contacts 128 include several power contacts and several signal contacts. The ground contacts 126 and the non-ground contacts 128 are both located on the active surface 122.
The first bonding wires 130 electrically connect the ground contacts 126 to the bus bars 116. The second bonding wires 132 electrically connect the bus bars 116 to the ground leads of the inner leads 114. The third bonding wires 134 electrically connect the other inner leads 114 to their corresponding second contacts 128. The die pad 112, the inner leads 114, the bus bars 116, the chip 120, the first bonding wires 130, the second bonding wires 132 and the third bonding wires are wrapped inside the encapsulant 140.
It should be noted that the inner leads 114 and the bus bars 116 in the conventional chip package structure 100 are coplanar. Therefore, the third bonding wires 134 must jump over the bus bar 116. In other words, the third bonding wires 134 have to rise to a greater height. As a result, the third bonding wires will be subjected to a greater pull by the encapsulant 140 during the encapsulating process. Ultimately, a greater number of third boding wires 134 is shifted or broken.